ASAP2010

ASAP 2010 — 21st IEEE International Conference on
Application-specific Systems, Architectures and Processors

July 7-9, 2010 †Rennes, France

LicesPort MordelaisJacquet

Wednesday 7

Thursday 8

Friday 9

08:20

WELCOME CEREMONY

KEYNOTE

APPLICATION SPECIFIC ARCHITECTURES

08:20

08:45

KEYNOTE

08:45

09:10

DESIGN AND PROGRAMMING OF ARRAY ARCHITECTURES

09:10

09:35

MAPPING FOR MULTI-CORE ARCHITECTURES

09:35

10:00

10:00

10:25

Coffee Break

POSTER SESSION

(and coffee break)

10:25

10:50

Coffee Break

APPLICATION SPECIFIC PROCESSORS

10:50

11:15

DESIGN SPACE EXPLORATION

11:15

11:40

POWER AWARE ARCHITECTURES

11:40

12:05

12:05

12:30

Lunch

Lunch

12:30

13:00

Lunch

13:00

13:30

13:30

14:00

SYSTEMS-ON-CHIP AND NETWORKS-ON-CHIP

COMPUTER ARITHMETICS AND CRYPTOGRAPHY

14:00

14:25

14:25

14:50

14:50

15:15

15:15

15:40

POSTER SESSION

(and coffee break)

15:40

16:05

Bus to

Le Mont Saint-Michel

16:05

16:30

16:30

16:55

FORMAL METHODS

16:55

17:20

Excursion to

Le Mont Saint-Michel

17:20

17:45

17:45

18:10

Bus to City Centre

18:10

18:30

Reception (City Hall)

18:30

19:00

Conference Banquet

19:00

20:00

20:00

21:00

21:00

22:00

22:00

23:00

23:00


Wednesday, July 7th†††††††††††††††††††††††††††††††††††††††††††††††††††††††††††† RENNES

8h20 - 8h45†††††††††††††††††† Welcome

8h45 - 9h35†††††††††††††††††† Keynote: †††† Convergence of Design and Fabrication Technologies, a Key Enabler for HW-SW Integration

††† Ahmed Jerraya

9h35 - 10h50†††††††††††††††† Mapping for Multi-Core Architectures

†††††††††††††††††††††††††††††††††††††††† Chair: Jeremy Buhler

††††† Dynamic Code Mapping for Limited Local Memory Systems

Seung chul Jung, Aviral Shrivastava, and Ke Bai

††††† Design of an Automatic Target Recognition Algorithm on the IBM Cell Broadband Engine

Weijia Che and Karam S. Chatha

††††† Highly Efficient Mapping of the Smith-Waterman Algorithm on CUDA-compatible GPUs

Keisuke Dohi, Khaled Benkrid, Cheng Ling, Tsuyoshi Hamada and Yuichiro Shibata

10h50 – 11h15†††††††††††† Coffee Break

11h15 - 12h30††††††††††††† Design Space Exploration

†††††††††††††††††††††††††††††† Chair: Krzysztof Kuchcinski

††††† ImpEDE: A Multidimensional, Design-Space Exploration Framework for Biomedical-Implant Processors

Dhara Dave, Christos Strydis and Georgi N. Gaydadjiev

††††† Design Space Exploration of Parametric Pipelined Designs

Adrien Le Masle and Wayne Luk

††††† Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect

Tung Thanh Hoang, Ulf Jšlmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Sjšlander, and Per Larsson-Edefors

12h30 – 14h00†††††††††††† Lunch


14h00 - 15h40††††††††††††† Systems-On-Chip and Networks-On-Chip

†††††††††††††††††††††††††††††† Chair: Steven Derrien

††††† Using Shared Library Interposing for Transparent Application Acceleration in Systems with Heterogeneous Hardware Accelerators

Tobias Beisel, Manuel Niekamp and Christian Plessl

††††† Enhancing Performance of Network-on-Chip Architectures with Millimeter-Wave Wireless Interconnects

Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Pande,Benjamin Belzer and Deuk Heo

††††† A Bayesian Network-Based Framework with Constraint Satisfaction Problem (CSP) Formulations for FPGA System Design

Amelia W. Azman, Abbas Bigdeli,Yasir Mohd-Mustafah, Morteza Biglari-Abhari and Brian C. Lovell

††††† An Optimized NoC Architecture for Accelerating TSP Kernels in Breakpoint Median Problem

Turbo Majumder, Souradip Sarkar, Partha Pande and Anantharaman Kalyanaraman

15h40 - 16h55††††††††††††† POSTER SESSION (and coffee break)ļ

Chair: FranÁois Charot††††††††††††††††††

††††† Hardware-Assisted Middleware: Acceleration of Garbage Collection Operations

Jie Tang, Shaoshan Liu, Zhimin Gu , Xiao-Feng Li, and Jean-Luc Gaudiot

††††† Flexible Hardware/Software Co-design for Scalable Elliptic Curve Cryptography for Low end Applications

Mohamed N Hassan, Mohammed Benaissa andAnstatus Kanakis

††††† An Efficient Computation Model for Coarse Grained Reconfigurable Architectures and its Applications to a Reconfigurable Computer

Oguzhan Atak and Abdullah Atalar

††††† Potential of using Block Floating Point Arithmetic in ASIP-Based GNSS-Receivers

Emrah Tasdemir, GŲtz Kappen andNoll Tobias G.

††††† Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution

Jimit Shah, Komanduri S. Raghunandan and Kuruvilla Varghese

††††† Memoryless RNS-to-Binary Converters for the { 2 n + 1 − 1, 2 n , 2 n − 1} Moduli Set

Kazeem Alagbe Gbolagade, George Razvan Voicu and Sorin Dan Cotofana

††††† A Pipelined Camellia Architecture for Compact Hardware Implementation

Elif Bilge Kavun and Tolga Yalcin

††††† General-purpose FPGA Platform for Efficient Encryption and Hashing

Jakub Szefer, Yu-Yuan Chen and Ruby B. Lee

††††† A compact FPGA-based Architecture for Elliptic Curve Cryptography over Prime Fields

Jo Vliegen, Nele Mentens, Jan Genoe, An Braeken, Serge Kubera, Abdellah Touhafi and Ingrid Verbauwhede

16h55 - 18h10††††††††††††† Formal Methods

††††††††††††††††††††††††††††††††††††††††††††††††††††††††††††† Chair: JŁrgen Teich

††††† A Formal Specification of Fault-Tolerance in Prospecting Asteroid Mission with Reactive Autonomic Systems Framework

Heng Kuang, Olga Ormandjieva, Stan Klasa and Jamal Bentahar

††††† Comparing the Robustness of Fault-Tolerant Enhancements When Applied to Lookup Tables and Random Logic for Nano-Computing

Yocheved Dotan, Orgad Chen, Gil Katz and David Lilja

††††† Dependability Analysis of a Countermeasure against Fault Attacks by means of Laser Shots onto a SRAM-based FPGA

Gaetan Canivet, Paolo Maistri, Regis Leveugle, Frederic Valette, Jessy Clediere and Marc Renaudin

18h10 – 18h30†††††††††††† Bus to City Centre

18h30 – 21h00†††††††††††† Reception (City Hall)


Thursday, July 8th†††††††††††††††††††††††††††††††††††††††††††††††††††††††††††††††† RENNES

8h20 - 9h10†††††††††††††††††† Keynote: The Light at the end of the CMOS Tunnel

Sani R. Nassif

9h10 - 10h25†††††††††††††††† Design and Programming of Array Architectures

††††††††††††††††††† ††††††††††† Chair: Patrice Quinton

††††† Modeling and Synthesis of Communication Subsystems for Loop Accelerator Pipelines

Hritam Dutta, Frank Hannig, Moritz Schmid, and Joachim Keinert

††††† Design of Throughput-Optimized Arrays from Recurrence Abstractions

Arpith C. Jacob, Jeremy C. Buhler and Roger D. Chamberlain

††††† A C++-Embedded Domain-Specific Language for Programming the MORA Soft Processor Array

Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti and Sohan Purohit

10h25 – 10h50†††††††††††† Coffee Break

10h50 - 12h30††††††††††††† Application Specific Processors

†††††††††††††††††††††††††††††† Chair: Frank Hannig

††††† A Forwarding-sensitive Instruction Scheduling Approach to Reduce Register File Constraints in VLIW Architectures

Guillermo PayŠ-VayŠ, Javier MartŪn-Langerwerf, Holger Blume and Peter Pirsch

††††† Dual-Purpose Custom Instruction Identification Algorithm based on Particle Swarm Optimization

Mehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, and Hamid Noori

††††† Combined Scheduling and Instruction Selection for Processors with Reconfigurable Cell Fabric

Antoine Floch, Christophe Wolinski and Krzysztof Kuchcinski

††††† Completeness of Automatically Generated Instruction Selectors

Florian Brandner

12h30 – 14h00†††††††††††† Lunch


14h00 - 16h05††††††††††††† Computer Arithmetics and Cryptography

†††††††††††††††††††††††††††††† Chair: Arnaud Tisserand

††††† Implementation of Binary Edwards Curves for very-constrained Devices

‹nal Kocabacs, Junfeng Fan and Ingrid Verbauwhede

††††† Elliptic Curve Point Multiplication on GPUs

Samuel Ant„o, Jean-Claude Bajard and Leonel Sousa

††††† Newton-Raphson Algorithms for Floating-Point Division Using an FMA

Nicolas Louvet, Jean-Michel Muller and Adrien Panhaleux

††††† An FPGA-Specific Algorithm for Direct Generation of Multi-Variate Gaussian Random Numbers

David B. Thomas and Wayne Luk

††††† Automatic Generation of Polynomial-based Hardware Architectures for Function Evaluation

Florent de Dinechin, Mioara Joldes and Bogdan Pasca

16h05 – 17h20†††††††††††† Bus to Le Mont Saint-Michel

17h20 – 19h00†††††††††††† Excursion to Le Mont Saint-Michel

19h00 – 23h00†††††††††††† Conference Banquet


Friday, July 9th†††††††††††††††††††††††††††††††††††††††††††††††††††††††††††††††† RENNES

8h20 - 10h25†††††††††††††††† Application Specific Architectures

†††††††††††††††††††††††††††††† Chair: Wayne Luk

††††† A Fully-Overlapped Multi-Mode QC-LDPC Decoder Architecture for Mobile WiMAX Applications

Bo Xiang, Dan Bao, Shuangqu Huang, and Xiaoyang Zeng

††††† High Parallel Variation Banyan Network Based Permutation Network for Reconfigurable LDPC Decoder

Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara and Satoshi Goto

††††† A High Efficient Memory Architecture for H.264 Motion Compensation

Chunshu Li, Kai Huang, Jiong Feng, Xiaolang Yan, Jiong Feng, De Ma, and Haitong Ge

††††† FPGA-based Lossless Compressors of Floating-Point Data Streams to Enhance Memory Bandwidth

Kazuya Katahira, Kentaro Sano and Satoru Yamamoto

10h25 - 11h40††††††††††††† POSTER SESSION (and coffee break)†

†††††††††††††††††††††††††††††† Chair: Christophe Wolinski

††††† Implementing Decimal Floating-Point Arithmetic through Binary: some Suggestions

Nicolas Brisebarre, Nicolas Louvet, Erik Martin-Dorel, Jean-Michel Muller, Adrien Panhaleux, and Milos Ercegovac

††††† A New Approach in On-line Task Scheduling for Reconfigurable Computing Systems

Maisam Mansub Bassiri and Hadi Shahriar Shahhoseini

††††† Exploring Algorithmic Trading in Reconfigurable Hardware

Stephen Wray, Wayne Luk and Peter Pietzuch

††††† Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators An Experience With the Altera C2H HLS Tool

Christophe Alias, Alain Darte, and Alexandru Plesco

††††† Deadlock Avoidance for Streaming Applications with Split-Join Structure: Two Case Studies

Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain and Joseph M. Lancaster

††††† Customizing Controller Instruction Sets for Application-Specific Architectures

Jian Li, David Dickin and Lesley Shannon

††††† Loop Transformations for Interface-based Hierarchies in SDF Graphs

Jonathan Piat, Shuvra S. Bhattacharyya and Mickael Raulet

††††† Code Generation for Hardware Accelerated AES

Raymond Manley, Paul Magrath and David Gregg

††††† Function Flattening for Lease-Based, Information-Leak-Free Systems

Xun Li, Mohit Tiwari, Tim Sherwood and Frederic T. Chong

11h40 - 13h00††††††††††††† Power Aware Architectures

†††††††††††††††††††††††††††††† Chair: Lesley Shannon

††††† Power Dissipation Challenges in Multicore Floating-Point Units

Wei Liu and Alberto Nannarelli

††††† On Energy Efficiency of Reconfigurable Systems with Run-Time Partial Reconfiguration

Shaoshan Liu, Richard Neil Pittman, Alessandro Forin and Jean-Luc Gaudiot

††††† A GALS FFT Processor with Clock Modulation for Low-EMI Applications

Xin Fan, Milos Krstic, Christoph Wolf, and Eckhard Grass

13h00 - 14h30†††††††††††††††† Lunch


ASAP 2010 is organized by

IEEE

ASAP 2010 is sponsored by

Irisa
IRISA
IRISA
Ville de Rennes
INRIA


Site last modified 2010-06-08