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ASAP 2009: Advance
Program
Sessions: Rooms Carver One & Two
Lunches & Receptions: Room Carver Three
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Tuesday
July 7, 2009
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7:45am
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Registration and Breakfast
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8:30am
- 9:30am
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Keynote speech
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Grand Challenges in Computational Systems Biology
Dr. Jeffrey Skolnick
Georgia Institute of Technology
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9:30am
- 10:45am
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Session
1: Arithmetic
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Chair:
Milos Ercegovac, UCLA
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Division
Unit for Binary Integer Decimals
Tomas Lang1 and Alberto Nannarelli2
1UC Irvine, 2Technical Univ. of Denmark
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A
Combined Decimal and Binary Floating-point Multiplier
Charles Tsen1, Sonia Gonzalez-Navarro2, Michael
Schulte1, Brian Hickmann3, Katherine
Compton1
1University of Wisconsin - Madison, 2Universidad de
Málaga, 3Intel Corporation
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Parallel
Prefix Ling Structures for Modulo 2n - 1 Addition
Jun Chen and James Stine
Oklahoma State University
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10:45am
- 11:15am
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Break
/ View Posters
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Integral
Parallel Architecture & Berkeley's Motifs
Mihaela Malita1 and Gheorghe Stefan2
1Saint Anselm College, NH, 2BrightScale, CA
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Application
Specific Transistor Sizing for Low Power Full Adders
Amirali Baniasadi
University of Victoria
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Reconfigurable
SWP operator for multimedia processing
Shafqat Khan, Emmanuel Casseau, Daniel Menard
IRISA INRIA
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Filtering Global History: Power and Performance Efficient Branch Predictor
Raid Ayoub, Alex Orailoglu
University of California, San Diego
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Efficient
Implementation of Carry-save adders in FPGA
Javier Hormigo1, Manuel A. Ortiz2, Francisco
Quiles2, Francisco J. Jaime1, Julio
Villalba1, Emilio L. Zapata1
1University of Malaga, 2University of Cordoba
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Acceleration
of Multiresolution Imaging Algorithms: A Comparative Study
Richard Membarth, Philipp Kutzer, Hritam
Dutta, Frank Hannig, Juergen Teich
University of Erlangen-Nuremberg
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11:15am
- 12:05pm
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Session
2: FPGA Applications I
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Chair:
Xinming Huang, Worcester Polytechnic Institute
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A
FPGA-based Parallel Architecture for Scalable High-Speed Packet
Classification
Weirong Jiang and Viktor Prasanna
University of Southern California
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Implementing
a Highly Parameterized Digital PIV System On Reconfigurable Hardware
Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor
Northeastern University
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12:05pm
- 2:00pm
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Lunch
/ View Posters
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2:00pm
- 3:15pm
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Session
3: Media and Image Processing
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Chair: Mark Franklin, Washington University in St. Louis
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Improving
VLIW Processor Performance using Three-Dimensional (3D) DRAM Stacking
Yangyang Pan and Tong Zhang
Rensselaer Polytechnic Institute
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Specialization
of the Cell SPE for Media Applications
Cor Meenderinck and Ben Juurlink
Delft University of Technology
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A
Massively Parallel Coprocessor for Convolutional Neural Networks
Murugan Sankaradas, Venkata Jakkula, Srihari
Cadambi, Srimat Chakradhar, Igor
Durdanovic, Eric Cosatto, Hans Peter Graf
NEC Laboratories America, Inc.
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3:15pm
- 3:45pm
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Break
/ View Posters
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3:45pm
- 5:00pm
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Session
4: FPGA Applications II
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Chair: Martin
Herbordt, Boston University
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An
FPGA-based Parallel Hardware Architecture for Real-time Face Detection
using a Face Certainty Map
Seunghun Jin1, Dongkyun Kim1, Thuy
Toung Nguyen1, Bongjin Jun2, Daijin
Kim2, Jae Wook Jeon1
1Sungkyunkwan Univ., 2Postech
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Accelerating
a Virtual Ecology Model with FPGAs
Julien Lamoureux, Tony Field, Wayne Luk
Imperial College
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Parallelized
Architecture of Multiple Classifiers for Face Detection
Junguk Cho1, Bridget Benson1, Shahnam
Mirzaei2, Ryan Kastner1
1University of California, San Diego, 2University of
California, Santa Barbara
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5:30pm - 10pm
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Harbor
Cruise
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*** Bus boarding at 5:30pm ***
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Wednesday
July 8, 2009
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8:00am
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Registration and Breakfast
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8:30am
- 9:30am
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Keynote speech
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Got Game? Experiences with a Cluster of Over 330 PS3s
Dr. Richard Linderman
Air Force Research Laboratory
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9:30am
- 10:45am
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Session
5: Arithmetic and Cryptography
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Chair:
James
Stine,
Oklahoma State University
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Design
and Implementation of a Radix-4 Complex Division Unit with Prescaling
Pouya Dormiani1, Milos Ercegovac1, Jean-Michel
Muller2
1University of California at Los Angeles, 2Ecole
Normale Superieure de Lyon
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A
Low Power High Performance Radix-4 Approximate Squaring Circuit
Satyendra Datla1, Mitchel Thornton2, David
Matula2
1TI, Dallas TX, 2SMU, Dallas, TX
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A
Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
Abdulhadi Shoufan1, Thorsten Wink1, Gregor
Molter1, Sorin Huss1, Falko
Strenzke2
1TU Darmstadt, 2Flexsecure
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10:45am
- 11:15am
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Break
/ View Posters
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An
Efficient Hardware Architecture for Spectral Hash Algorithm
Ray C.C. Cheung1, Cetin Kaya Koc2, John
D. Villasenor1
1UCLA, 2UCSB
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P3FSM:
Portable Predictive Pattern Matching Finite State Machine
Lucas Vespa, Mini Mathew, Ning Weng
Southern Illinois University
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Run-Time
Detection of Malwares via Dynamic Control-Flow Inspection
Yong-Joon Park1, Zhao Zhang1, Songqing
Chen2
1Department of Electrical and Computer Engineering, Iowa State
University, 2Department of Computer Science, George Mason
University
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A
Sixteen-context Optically Reconfigurable Gate Array
Mao Nakajima and Minoru Watanabe
Shizuoka University
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Mapping
Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable
Architecture
Cao Liang and Xinming Huang
Worcester Polytechnic Institute
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An
Area-Efficient LDPC Decoder Architecture and Implementation for CMMB
Systems
Kai Zhang1, Xinming Huang1, Zhongfeng
Wang2
1Worcester Polytechnic Institute, 2Broadcom
Corporation
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11:15am
- 12:05pm
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Session
6: Application-Specific Integrated Circuits
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Chair:
Frank Hannig, University of Erlangen‐Nuremberg
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An
Input Triggered Polymorphic ASIC for H.264 Decoding
Adarsha Rao1, Mythri Alle1, Sainath
V1, Reyaz Shaik1, Rajashekhar
Chowhan1, Sankaraiah S1, Sravanthi
Mantha1, Nandy S. K.1, Ranjani
Narayan2
1Indian Institute of Science, 2Morphing Machines Pvt.
Ltd.
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Power-scalable
Reconfigurable Switch-Based FFT Processor
Bassam Mohd1 and Earl Swartzlander, Jr.2
1Qualcomm, Inc, 2University of Texas-Austin
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12:05pm
- 2:00pm
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Lunch
/ View Posters
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1:30pm
- 2:00pm
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Invited Talk
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FPGA-based RTL Emulation for Embedded Software Development
Rich Claggett
EVE-USA
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2:00pm
- 3:15pm
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Session
7: Computational Biology
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Chair:
Jeremy Buhler,
Washington University in St. Louis
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MSA-CUDA:
Multiple Sequence Alignment on Graphics Processing Units with CUDA
Yongchao Liu, Bertil Schmidt, Douglas Maskell
School of Computer Engineering, Nanyang Technolgical University, Singapore
639798
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Parallel Discrete Event Simulation
of Molecular Dynamics Through Event-Based Decomposition
Martin Herbordt, Ashfaq Khan, Tony Dean
Boston University
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NeMo:
A Platform for Neural Modelling of Spiking Neurons Using GPUs
Andreas Fidjeland, Etienne Roesch, Murray
Shanahan, Wayne Luk
Imperial College London
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3:15pm
- 3:45pm
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Break
/ View Posters
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3:45pm
- 5:15pm
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Panel
Session
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Multi-Core/Threaded Processors vs Diverse Component Integrated Systems
| Organizer: |
Mark Franklin |
Washington Univ. in St. Louis |
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Panelists: |
Wayne Luk |
Imperial College, London |
| Brian Ogilvie |
Mathworks |
| Jeremy Buhler |
Washington Univ. in St. Louis |
| Jay Wilkinson |
Intel |
| Michael Champigny |
Mercury Computer Systems |
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6:00pm - 8:00pm
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Demo
Night
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Thursday
July 9, 2009
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8:00am
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Registration and Breakfast
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8:30am
- 9:45am
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Session
8: Tools and Design Aids
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Chair:
Xinming Huang, Worcester Polytechnic Institute
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Constraint-Driven
Instructions Selection and Application Scheduling in the DURASE system
Kevin Martin1, Christophe Wolinski1, Krzysztof
Kuchcinski2, Antoine Floch1, Francois
Charot1
1University of Rennes I, Irisa, Inria, France, 2Dept.
of Computer Science, Lund University, Sweden
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A
System Framework for the Design of Embedded Software Targeting
Heterogeneous Multi-Core SoCs
Xavier Guérin and Frédéric Pétrot
TIMA Laboratory
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Impact
of Loop Tiling on the Controller Logic of Hardware Acceleration Engines
Hritam Dutta, Jiali Zhai, Frank
Hannig, Juergen Teich
University of Erlangen-Nuremberg
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10:15am
- 11:30am
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Session
9: Application-Specific Instruction Processors
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Chair:
Miriam
Leeser,
Northeastern University
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Evaluating
Various Branch-prediction Schemes for Biomedical-implant Processors
Christos Strydis and Georgi Gaydadjiev
TU Delft
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Low-Power
ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
Andreas Genser1, Christian Bachmann1, Christian
Steger1, Jos Hulzink2, Mladen
Berekovic3
1Institute for Technical Informatics, Graz University of
Technology, Austria, 2IMEC NL, Holst Centre Eindhoven, The
Netherlands, 3Technical University Braunschweig, Germany
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Scalar
Processing Overhead on SIMD-Only Architectures
Arnaldo Azevedo and Ben Juurlink
TU Delft
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11:30am
- 11:45pm
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Wrap-Up
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