Session 1: Application-Specific Processor Instruction Sets

Chair: Dake Liu

Fast Custom Instruction Identification by Convex Subgraph Enumeration.
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can Ozturan  and Gunhan Dundar

Bit Matrix Multiplication in Commodity Processors.
Yedidya Hilewitz, Cédric Lauradoux and Ruby Lee

Synthesis of Application Accelerators on Runtime Reconfigurable Hardware.
Mythri Alle, Keshavan Varadarajan, Ramesh Reddy, Nimmy  Joseph, Alexander Fell,
 Adarsha Rao, S K Nandy and Ranjani Narayan

Floating Point Multiplication Rounding Schemes for Interval Arithmetic.
Alexandru Amaricai, Mircea Vladutiu, Mihai Udrescu,  Lucian Prodan and Oana Boncalo

Fast Multivariate Signature Generation in Hardware: The Case of Rainbow.
Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp,  Jintai Ding and Harold W Carter

Fault-Tolerant Dynamically Reconfigurable NoC-based SoC.
Mohammad Hosseinabady and Jose Nunez-Yanez

Security Processor with Quantum Key Distribution.
Thomas Lorünser, Edwin Querasser, Thomas Matyus,  Momtchil Peev, Johannes Wolkerstorfer, 
Michael Hutter, Alexander Szekely, Ilse  Wimberger, Christian Pfaffel-Janser and Andreas Neppach

Fully-Pipelined Efficient Architectures for FPGA Realization of Discrete Hadamard Transform.
Pramod Meher and J C Patra

Reconfigurable Viterbi Decoder on Mesh Connected Multiprocessor Architecture.
Ritesh Rajore, Ganesh Garga, S K Nandy and Jamadagni H  S

Run-time thread sorting to expose data-level parallelism.
Tirath Ramdas, Gregory Egan, David Abramson and Kim  Baldridge

Session 2: System-level Interconnect and Mapping in SoCs

Chair: Yvon Savaria

A New High-Performance Scalable Dynamic Interconnection for FPGA-based Reconfigurable Systems.
Slavisa Jovanovic, Camel Tanougast and Serge Weber

Extending the SIMPPL SoC Architectural Framework to Support Application-Specific Architectures on Multi-FPGA Platforms.
David Dickin and Lesley Shannon

PERMAP: A Performance-Aware Mapping for Application-Specific SoCs.
A. E. Kiasari, S. Hessabi and H. Sarbazi-Azad

Session 3: Advances in Cryptography

Chair: Christopher Wolf

Low-cost Implementations of NTRU for pervasive security.
Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede and S. Berna Ors Yalcin

On the High-Throughput Implementation of RIPEMD-160 Hash Algorithm.
Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee and  Ingrid Verbauwhede

Zodiac: System Architecture Implementation for a High-Performance Network Security Processor.
Haixin Wang, Guoqiang Bai and Hongyi Chen

Session 4: New Computational Methods

Chair: Georgi Kuzmanov

Efficient Systolization of Cyclic Convolution for Systolic Implementation of Sinusoidal Transforms
Pramod Meher

Resource Efficient Generators for the Floating-point Uniform and Exponential Distributions
David Barrie Thomas and Wayne Luk

Low Discrepancy Sequences for Monte Carlo Simulations on Reconfigurable Platforms
Ishaan Dalal,  Deian Stefan and Jared Harwayne-Gidansky

Session 5: Novel Applications

Chair: David Thomas

A Subsampling Pulsed UWB Demodulator Based on a Flexible Complex SVD.
Yves Vanderperren and Wim Dehaene

Dynamically Reconfigurable Regular Expression Matching Architecture.
Divyasree J, Rajashekar H and Kuruvilla Varghese

An MPSoC Architecture for the Multiple Target Tracking Application in Driver Assistant System.
Jehangir Khan, Smail Niar, Yassin Elhillali, Atika  Rivenq-Menhaj and Jean-Luc Dekeyser

Session 6: New Directions in Application-Specific Design

Chair: Lesley Shannon

High-Level Energy Estimation and Analysis of RF-Powered Devices.
Manuel Wendt and  Matthias Grumer

Managing Multi-Core Soft-Error Reliability Through Utility-driven Cross Domain Optimization.
Wangyuan Zhang and  Tao Li 

An Efficient Implementation Of A Phase Unwrapping Kernel On Reconfigurable Hardware.
Sherman Braganza and Miriam Leeser

A Parallel Hardware Architecture for Connected Component Labeling Based on Fast Label Merging.
Holger  Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann and Peter  Pirsch

Operation Shuffling over Cycle Boundaries for Low Energy L0 Clustering.
Yuki Kobayashi,  Murali Jayapala, Praveen Raghavan, Francky Catthoor and Masaharu Imai

An Efficient Digital Circuit for Implementing Sequence Alignment Algorithm in an Extended Processor.
Vamsi Kundeti, Yunsi Fei and Sanguthevar Rajasekaran

Concurrent Systolic Architecture for High-Throughput Implementation of 3-Dimensional DWT.
Basant K Mohanty and Pramod Meher

Hierarchical Design Space Exploration of a Cooperative MIMO Receiver for Reconfigurable Architectures.
Shahnam Mirzaei, Ryan  Kastner, Ali Irturk, Brad Weals and Richard Cagley

A dynamic holographic reconfiguration on a four-context ODRGA.
Mao Nakajima and  Minoru Watanabe

FGPA-based hardware accelerator of the heat equation with applications on infrared thermography
Fernando  Pardo Seco, Paula López Martínez and Diego Cabello Ferrer

FPGA Based Singular Value Decomposition for Image Processing Applications.
Masih Rahmati,  Mohammad Sadegh Sadri and Mehdi Ataei Naeini

Session 7: Acceleration of aScientificnd DSP Applications

Chair: Joseph Cavallaro

Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs.
Arpith Jacob, Jeremy  Buhler and Roger Chamberlain

A Multi-FPGA Application-Specific Architecture for Accelerating a Floating Point Fourier Integral Operator.
Jason Lee, Lesley  Shannon, Matthew Yedlin and Gary Margrave

Reconfigurable Acceleration of Microphone Array Algorithms for Speech Enhancement.
Ka Fai Cedric Yiu,  Chun Hok Ho, Nedelko Grbic, Yao  Lu, Xiaoxiang Shi and Wayne Luk

Session 8: Advanced Communications Applications

Chair: Praveen Raghavan

Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards.
Yang Sun, Yuming Zhu,  Manish Goel and Joseph Cavallaro

Architecture and VLSI Realization of a High-Speed Programmable Decoder for LDPC Convolutional Codes.
Marcos B.S. Tavares,  Steffen Kunze, Emil Matus and Gerhard P. Fettweis

Buffer allocation for Advanced Packet Segmentation in Network Processors.
Daniel Llorente,  Kimon Karras, Thomas Wild and Andreas Herkersdorf

Session 9: Arithmetic

Chair: Lejla Batina

New Insights on Ling Adders.
Alvaro  Vázquez and Elisardo Antelo

Integer and Floating-Point Constant Multipliers for FPGAs.
Nicolas  Brisebarre, Florent de Dinechin and Jean-Michel Muller

An Efficient Method for Evaluating Polynomial and Rational Function Approximations.
Nicolas  Brisebarre, Sylvain Chevillard, Milos Ercegovac, Jean-Michel Muller and Serge  Torres

Session 10: Interconnect and Mapping

Chair: Dirk Stroobandt

Mapping of the AES Cryptographic Algorithm on a Coarse-Grain Reconfigurable Array Processor.
Andres  Garcia, Mladen Berekovic and Tom Vander Aa

RECONNECT: A NoC for polymorphic ASICs using a Low Overhead Single Cycle Router.
Nimmy Joseph, Ramesh Reddy  C, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S K Nandy and Ranjani  Narayan

Loop-Oriented Metrics for Exploring and Application-Specific Architecture Design-Space
Maria Mbaye, Normand  Bélanger, Yvon Savaria and Samuel Pierre

Session 11: Novel Processor and Memory System Techniques

Chair: Tom Vander Aa

Rapid Estimation of Instruction Cache Hit Rates Using Loop Profiling.
Santanu Kumar Dash and Srikanthan Thambipillai

Reducing Power Consumption of Embedded Processors through Register File Partitioning and Compiler Support.
Xuan Guan and Yunsi Fei

Lightweight DMA Management Mechanisms for Multiprocessors on FPGA.
Antonino Tumeo, Matteo Monchiero, Gianluca  Palermo, Fabrizio Ferrandi and Donatella Sciuto 

Memory Copies in Multi-Level Memory Systems.
Pepijn de Langen and Ben Juurlink 

Session 12: Image and Video Processing

Chair: Murali Jayapala

Architecture of a Polymorphic ASIC for interoperability across multi-mode H.264 decoders.
Adarsha Rao, Mythri A, S K Nandy and Ranjani  Narayan 

An FPGA Architecture for CABAC Decoding in Many-core Systems.
Roberto Osorio and Javier Bruguera 

Novel Approach on Lifting-Based DWT and IDWT Processor with Multi-Context Configuration to Support Different Wavelet Filters.
Andre Guntoro and Manfred Glesner 

Throughput-Scalable Hybrid-Pipeline Architecture for Multilevel Lifting 2-D DWT of JPEG 2000 Coder.
Basant K Mohanty and Pramod Meher

Lunch